1. Field of the Invention
This invention relates generally to the electronic arts and more particularly to circuits for detecting clock loss and effecting switchover of clock signals.
2. Description of Related Art
Many electronic devices, including programmable logic devices, utilize clock signals. Programmable logic devices (“PLDs”) (also sometimes referred to as PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, or FPGAs), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits; however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
Clock signals may be generated internally or externally to the electronic device. In some instances, it may be desirable to provide two or more clock signals that may be used alternatively. One reason for providing two or more alternate clock signals may be to accomplish redundancy that allows operation to be maintained even if the primary clock signal utilized by the device is lost or otherwise not functioning properly. Another reason for providing two or more alternate clock signals may be to select between different frequencies for operating the device or a portion of the device. While it is known to provide for switchover on loss of a clock signal, there is also a need to provide flexibility in the same device to switch between clock signals for clock loss reasons on the one hand and user-determined reasons on the other. Furthermore, there is also a need for a simple digital clock loss detection circuit.